DK-DEV-5SGXEA7N【PDF 277/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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10-6

Supported JTAG Instruction

SV51012

2014.01.10

JTAG Instruction

LOCK

UNLOCK

KEY_CLR_VREG

KEY_VERIFY

EXTEST_PULSE

EXTEST_TRAIN

Altera Corporation

Instruction Code

01 1111 0000

11 0011 0001

00 0010 1001

00 0001 0011

00 1000 1111

00 0100 1111

Description

Put the device in JTAG secure mode.

In this mode, only BYPASS , SAMPLE /

PRELOAD , EXTEST , IDCODE ,

SHIFT_EDERROR_REG , and UNLOCK

instructions are supported. This

instruction can only be accessed

through JTAG core access in user

mode. It cannot be accessed through

external JTAG pins in test or user

mode.

Release the device from the JTAG

secure mode to enable access to all

other JTAG instructions. This instruc-

tion can only be accessed through

JTAG core access in user mode. It

cannot be accessed through external

JTAG pins in test or user mode.

Clears the volatile key.

Verifies the non-volatile key has been

cleared.

Enables board-level connectivity

checking between the transmitters and

receivers that are AC coupled by

generating three output transitions:

? Driver drives data on the falling

edge of TCK in the UPDATE_IR/DR

state.

? Driver drives inverted data on the

falling edge of TCK after entering the

RUN_TEST/IDLE state.

? Driver drives data on the falling

edge of TCK after leaving the

RUN_TEST/IDLE state.

The EXTEST_PULSE JTAG instruction

is only supported in user mode for

Stratix V devices.

Behaves the same as the EXTEST_PULSE

instruction except that the output

continues to toggle on the TCK falling

edge as long as the TAP controller is in

the RUN_TEST/IDLE state.

The EXTEST_TRAIN JTAG instruction

is only supported in user mode for

Stratix V devices.

JTAG Boundary-Scan Testing in Stratix V Devices

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